CY29973 buffer equivalent, 3.3v 125-mhz multi-output zero delay buffer.
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Output Frequency up to 125 MHz 12 Clock Outputs: Frequency Configurable 350 ps max. Output to Output Skew Configurable Output Disable.
the CY29973 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary .
44, 46, 48, 50 QA(3:0) 32, 34, 36, 38 QB(3:0) 16, 18, 21, 23 QC(3:0) 29 FB_OUT
25
SYNC
VDDC
O
42, 43 40, 41 19, 20 5, 26, 27 52 31 6 7 8 2
SELA(1,0) SELB(1,0) SELC(1,0) FB_SEL(2:0) VCO_SEL FB_IN PLL_EN REF_SEL TCLK_SEL MR#/OE
I I I I I I I I .
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